Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device has a gate electrode formed extending on a first and second gate insulation films formed on P type semiconductor substrate, an N+ type source region adjacent to one end of the gate electrode, an N−type drain region facing said source region through a channel region, having high impurity concentration peak at a position of the predetermined depth at least in said substrate under said first gate insulation film, and formed so that high impurity concentration becomes low at a region near surface of the substrate, an N− type drain region formed so as to range to the N− type drain region, an N+ type drain region separated from the other end of said gate electrode and included in said N− type drain region, and an N type layer formed so as to span from one end portion of said first gate insulation film to said N+ type drain region.

BACKGROUND OF THE INVENTION

[0001] 1. Fieled of the Invention

[0002] The present invention relates to a semiconductor device and amethod of manufacturing the device, particularly to technique improvingoperation sustaining voltage characteristic of high sustaining voltageMOS transistor for high voltage of power source (HV-VDD) used for an LCDdriver, an EL driver and so on.

[0003] 2. Description of the Related Art

[0004] A semiconductor device according to the related art will bedescribed below referring a section view of an LDD type high sustainingvoltage MOS transistor shown in FIG. 13.

[0005] In FIG. 13, a gate electrode 53 is formed on a P typesemiconductor substrate (P-Sub) 51 through a gate insulation film 52. AnN+ type source region 54 is formed so as to be adjacent to one end ofsaid gate electrode 53, an N− type drain region 56 is formed facing saidsource region 54 through a channel region and further separated from theother end of the gate electrode 53, and an N+ type drain region 57 isformed so as to be included in an N− type drain region 56.

[0006] In the prior art, a low concentration N− type drain region 56 isformed by thermal diffusion of about 1000° C. to 1100° C. so as to forma gentle slope and a deep diffusion layer.

[0007] However, even with such the construction, voltage between sourceand drain (BVDS: sustaining voltage at OFF) is high, but sustainingvoltage (VSUS: sustaining voltage at ON) being operation sustainingvoltage of the voltage is about 30 V at most in the prior art.

[0008] A mechanism decreasing the above-mentioned operation sustainingvoltage will be described below.

[0009] In such the N channel type high sustaining voltage MOStransistor, a horizontal bipolar transistor 60 having the drain region57 as corrector (N+), the source region 54 as emitter (N+), and thesemiconductor substrate 51 as base (P) is formed parasitically as shownin FIG. 14 and FIG. 15. Decreasing of operation sustaining voltage VSUSeven if voltage between source and drain BVDS being sustaining voltageat OFF is caused by ON of the parasitical bipolar transistor 60. Thus,operation range of the N channel type high sustaining voltage MOStransistor is limited and operation at all over the range is difficult.

[0010] An operation of said bipolar transistor 60 will be describedbelow.

[0011] AS shown in FIG. 14, gate voltage (VG)(>Vt: threshold voltage) isadded to the gate electrode 53, voltage of a drain electrode (VD) (>>VG)contacting the drain region 57 is added, and a positive feedback loopdescribed later (refer FIG. 16) is formed in the case of ON of the MOStransistor.

[0012] That is, {circle over (1)} avalanche multiplication generates ina depletion layer by electron of a channel region 62 accelerated at adepletion layer near the drain region 57 so as to generate a pair of anelectron and a hole. {circle over (2)} Said hole flows in the substrate(substrate current: ISub) {circle over (3)} Said substrate current(ISub) generates voltage slope in the semiconductor substrate 51 toraise substrate voltage. {circle over (4)} Junction between the sourceregion 54 and the substrate 51 is biased to forward direction. {circleover (5)} Electron is implanted from the source region 54 to thesubstrate 51. {circle over (6)} The implanted electron reaches the drainregion 57 and further occurs avalanche multiplication.

[0013] Thus, by forming the positive feedback of {circle over (1)} to{circle over (6)}, large current flows in the device so as to break thedevice.

[0014] Therefore, in design of the N channel type high sustainingvoltage MOS transistor, conditions of the design are set considering theabove-mentioned phenomenon. First, a transistor construction decreasingsubstrate current (ISub) is adopted because operation sustaining voltage(VSUS) becomes small as substrate current (ISub) becomes large, andsecond, the conditions are decided so as to decrease substrate current(ISub) at an actually used region.

[0015]FIG. 7 is a substrate current (ISub) vs. gate voltage (VG)characteristic view, in the figure, double humps characteristic ofsubstrate current (ISub) at high region in gate voltage (VG) rises aboutthe conventional N channel type high sustaining voltage MOS transistor(shown with a dotted line in the figure). Therefore, operationsustaining voltage (VSUS) is low as shown in drain current (ID) vs.drain voltage (VD) characteristic view of FIG. 8 and a characteristicview showing operation sustaining voltage of FIG. 9.

[0016] The double humps characteristic is caused by concentration ofelectric field by spreading the depletion layer near the N+ drain regionat high region in gate voltage (VG).

[0017] Although it is considered to increase ion implantation volume(doze) and to rise concentration of N− type drain region as shown inFIG. 9 to improve operation sustaining voltage (VSUS), the conventionalsemiconductor device is not improved enough in sustaining voltage asshown with white circles. Because concentration of end portion A of theN− type drain region 56 shown in FIG. 13 rises conversely, problems ofincrease of short channel effect by that depletion layer spreads to thechannel region 55 direction, increase of snap back phenomenon byincrease of peak value of substrate current (ISub), and further decreaseof voltage between source and drain (BVDS) occur. Therefore, there isnot effective means improving operation sustaining voltage.

[0018] Therefore, an object of the invention is to provide asemiconductor device capable of improving operation sustaining voltageand a method of manufacturing the device.

SUMMARY OF THE INVENTION

[0019] A semiconductor device of the invention has a gate electrodeformed extending on a first and second gate insulation films formed onone conductive type semiconductor substrate, a reverse conductive typesource region adjacent to one end of said gate electrode, a first lowconcentration reverse conductive type drain region formed facing saidsource region through a channel region, having high impurityconcentration peak at a position of the predetermined depth at least insaid substrate under said first gate insulation film, and formed so thathigh impurity concentration becomes low at a region near surface of thesubstrate, a second concentration reverse conductive type drain regionformed so as to range to the first low concentration reverse conductivetype drain region, and a third concentration reverse conductive typedrain region separated from the other end of said gate electrode andincluded in said second concentration reverse conductive type drainregion.

[0020] Thus, it is possible that the first concentration reverseconductive type drain region under the first gate insulation film wherethe gate electrode is formed lower in high impurity concentration thanthe second concentration reverse conductive type drain region of anactive region and electric field concentration at end portion of thegate electrode through the first gate insulation film is depressed so asto design high sustaining voltage.

[0021] A semiconductor device of the invention has high impurityconcentration peak at a position of the predetermined depth in saidsubstrate at a region spanning from one end of said first gateinsulation film to said third concentrate reverse conductive type drainregion, and the fourth concentration reverse conductive type layer isformed so that high impurity concentration becomes low at a region nearsurface of the substrate.

[0022] A method of manufacturing a semiconductor device has process forion-implanting a reverse conductive type impurity in the predeterminedregion of one conductive type semiconductor substrate, process forforming a first gate insulation film field-oxidizing the predeterminedregion of said substrate, forming a first concentration reverseconductive type drain region under the first gate insulation filmdiffusing said impurity ion-implanted, and forming a secondconcentration reverse conductive type drain region so as to range to thefirst concentration reverse conductive type drain region, process forforming a gate electrode so as to span from the first gate insulationfilm to the second gate insulation film after forming the second gateinsulation film on said substrate except said first gate insulationfilm, and process for forming a reverse conductive type source region soas to be adjacent to one end of said gate electrode, and forming a thirdconcentration reverse conductive type drain region facing said sourceregion through a channel region, separated from the other end of saidgate electrode, and included in said second concentration reverseconductive type drain region.

[0023] A method of manufacturing a semiconductor device has process forforming the fourth concentration reverse conductive type layer so as tospan from one end portion of said first gate insulation film to saidthird concentration reverse conductive type drain region after formingsaid third concentration reverse conductive type drain region.

[0024] A method of manufacturing a semiconductor device has process forforming a fourth concentration reverse conductive type layer having highimpurity concentration peak at a position of the predetermined depth insaid substrate at a region spanning from a position having thepredetermined space from one end portion of said first gate insulationfilm to said third concentration reverse conductive type drain region,and is formed so that high impurity concentration becomes low at aregion near surface of the substrate after forming said thirdconcentration reverse conductive type drain region.

[0025] A method of manufacturing a semiconductor device has said formingprocess of the fourth concentration reverse conductive type layerwherein phosphorus ion is ion-implanted with high acceleration energy ofabout 100 KeV to 200 KeV.

[0026] A method of manufacturing a semiconductor device has said formingprocess of the fourth concentration reverse conductive type layerwherein ion implantation is carried out at a region spanning from aposition separated the predetermined space from said first gateinsulation film to said third concentration reverse conductive typedrain region by using a photo-resist as a mask.

[0027] A method of manufacturing a semiconductor device has said formingprocess of the fourth concentration reverse conductive type layerwherein ion implantation is carried out at a region spanning from aposition separated the predetermined space from the first gateinsulation film to said third concentration reverse conductive typedrain region by using a side wall insulation film formed at a side wallportion of said first gate insulating film as a mask.

[0028] A method of manufacturing a semiconductor device has said formingprocess of the fourth concentration reverse conductive type layerwherein said fourth concentration reverse conductive type layer isformed at a region spanning from a position separated the predeterminedspace from the first gate insulation film to said third concentrationreverse conductive type drain region by ion implantation from obliqueupper side of the first gate insulation film by using said gateinsulation film as a mask.

[0029] A method of manufacturing a semiconductor device has said formingprocess of the fourth concentration reverse conductive type layerwherein said fourth concentration reverse conductive type layer isformed at a region spanning from a position separated the predeterminedspace from the first gate insulation film to said third concentrationreverse conductive type drain region by ion-implanting from obliqueupper side of the first gate insulation film by using a photo-resistformed so as to cover said first gate insulation film as a mask.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030]FIG. 1 is a first section view showing a method of manufacturing asemiconductor device of a first embodiment of the present invention.

[0031]FIG. 2 is a second section view showing a method of manufacturinga semiconductor device of a first embodiment of the present invention.

[0032]FIG. 3 is a third section view showing a method of manufacturing asemiconductor device of a first embodiment of the present invention.

[0033]FIG. 4 is a fourth section view showing a method of manufacturinga semiconductor device of a first embodiment of the present invention.

[0034]FIG. 5 is a view showing substrate concentration distribution ofthe semiconductor device of the first embodiment of the presentinvention.

[0035]FIG. 6 is a section view showing a method of manufacturing asemiconductor device of a second embodiment of the present invention.

[0036]FIG. 7 is a view showing substrate current (ISub) vs. gate voltage(VG) of a semiconductor device of the invention and the conventionalsemiconductor device.

[0037]FIG. 8 is a view showing drain current (ID) vs. drain voltage (VD)of a semiconductor device of the invention and the conventionalsemiconductor device.

[0038]FIG. 9 is a view showing operation sustaining voltage of asemiconductor device of the invention and the conventional semiconductordevice.

[0039]FIG. 10 is a section view showing a method of manufacturing asemiconductor device of a third embodiment of the present invention.

[0040]FIG. 11 is a section view showing a method of manufacturing asemiconductor device of a fourth embodiment of the present invention.

[0041]FIG. 12 is a section view showing a method of manufacturing asemiconductor device of a fifth embodiment of the present invention.

[0042]FIG. 13 is a section view showing the conventional semiconductordevice.

[0043]FIG. 14 is a section view of the semiconductor device fordescribing the mechanism of the conventional operation sustainingvoltage drop.

[0044]FIG. 15 is a view showing the equivalent circuit of theconventional parasitic bipolar transistor.

[0045]FIG. 16 is a view showing a positive feedback loop for describingthe mechanism of the conventional operation sustaining voltage drop.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] Embodiments of a semiconductor device and a method ofmanufacturing the same of the invention will be described belowreferring figures.

[0047] In a semiconductor device of a first embodiment according to theinvention, a first gate insulation film 4 and a second gate insulationfilm 6 are formed on one conductive type semiconductor substrate, forexample, P type semiconductor substrate (P-SuB) 1, and a gate electrode7 is formed so as to span from the first gate insulation film 4 to thesecond gate insulation film 6 as FIG. 4. A high concentration reverseconductive (N+) type source region 9 is formed so as to be adjacent toone end of said gate electrode 7, a first low concentration reverseconductive (N−−) type drain region 5A is formed so as to face saidsource region 9 through a channel region under the gate electrode 7, asecond low concentration reverse conductive (N−) type drain region 5B isformed so as to range to the first low concentration reverse conductive(N−−) type drain region 5A, and further, a high (third) concentrationreverse conductive (N+) type drain region 10 is formed so as to beseparated from the other end of said gate electrode 7 and included insaid second low concentration N− type drain region 5B.

[0048] Thus, a low concentration reverse conductive type drain region 5is formed so as to be high in high impurity concentration from the endof the gate electrode 7 to said third concentration reverse conductive(N+) type drain region 10. That is, the low concentration reverseconductive type drain region 5 is formed so that high impurityconcentration becomes high from the first low concentration reverseconductive (N−−) type drain region 5A to the second low concentrationreverse conductive (N−) type drain region 5B.

[0049] A method of manufacturing the above-mentioned semiconductordevice will be described below.

[0050] First, an ion implantation layer 3 is formed by ion-implanting Ntype impurity on a drain forming region on a P type semiconductorsubstrate 1 by using a photo-resist 2 as a mask as shown in FIG. 1. Inthe process, as the N type impurity, phosphorus ion (³¹P⁺) for exampleis ion-implanted with about 100 KeV in acceleration voltage and4×10¹²/cm² to 6×10¹²/cm² (6×10¹²/cm² in the embodiment) in implantationvolume.

[0051] Next, by field oxidation of the predetermined region of thesubstrate 1, a first gate insulation film 4 consisting of a fieldoxidation film of 800 nm thickness is formed as shown in FIG. 2. In theprocess, the field oxidation film is formed by field oxidation of about1000° C., 1 hour in N_(a) atmosphere and 5 hours in O_(a) atmosphere.

[0052] Next, in the process, phosphorus ion in said ion implantationlayer 3 is diffused, the first low concentration reverse conductive(N−−) type drain region 5A is formed under said first gate insulationfilm 4, and the second low concentration reverse conductive (N−) typedrain region 5B is formed so as to range to the first low concentrationreverse conductive (N−−) type drain region 5A.

[0053] Here, the semiconductor of the invention is characterized inion-implanting for forming an N type drain region before forming thefield oxidation film and letting between under the field oxidation film(the first gate insulation film 4) and an active region have impuritydistribution.

[0054] That is, a low concentration N type drain region 5 is formed at aregion including under the first gate insulation film 4 formed bywell-known LOCOS (Local oxidation of silicon) as shown in FIG. 2. Theunder part of the first gate insulation film 4 of the drain region 5 isformed low in impurity comparing with other region in the drain region5. First, by field oxidation after ion-implanting phosphorus ion (³¹P⁺)into a forming region of said drain region 5 with 4×10¹²/cm² to6×10¹²/cm² in implantation volume as above-mentioned, phosphorus ion(³¹P⁺) is taken in the first gate insulation film 4 at growth region ofsaid first gate insulation film 4 at oxidation, the low concentrationN−− type drain region 5A is formed under the first gate insulation film4, and the N− type drain region 5B rather higher in impurity than theN−− type drain region 5A is formed so as to range to the N−− type drainregion 5A (the other end of the first gate).

[0055] As described above, by field oxidation after ion-implantingphosphorus ion (³¹P⁺) at the forming region of said drain region 5 andion-implanting the P type impurity for forming the channel stopper layerunder the forming region of the first gate insulation film 4, Thephosphorus ion (³¹P⁺) is taken in the first gate insulation film 4 atthe growth part of said gate insulation film 4 at oxidation. Byion-implanting a reverse conductive P type impurity to phosphorus ion(for example, boron ion (¹¹B⁺), the low concentration N−− type drainregion is formed under the first gate insulation film 4. Further, sincethe process uses ion implantation process of the P type impurity forforming the channel stopper layer, number of manufacturing process isnot decreased and operation efficiency is good.

[0056] As shown in FIG. 3, by forming a conductive film, for example, apolysilicon film at the entire surface after forming the second gateinsulation film 6 of about 100 nm thickness carrying out thermaloxidation at region except the first gate insulation film 4 on saidsubstrate 1 and by patterning the polysilicon film using well-knownpatterning technique, the gate electrode 7 of 400 nm in thickness isformed so as to span from said first gate insulation film 4 to thesecond gate insulation film 6.

[0057] As shown in FIG. 4, arsenic ion (⁷⁵As⁺) for example ision-implanted on the predetermined region on a source forming region andsaid low concentration drain region 5 with 80 KeV in accelerationvoltage and about 6×10¹⁵/cm² in implantation volume by using aphoto-resist 8 having openings as a mask. A high concentration N+ typesource region 9 is formed so as to be adjacent to one end of said gateelectrode 7, and a high (third) concentration N+ type drain region 10separated from the other end of the gate electrode 7 and included insaid low concentration (n−) type drain region 5B is formed.

[0058] In concentration distribution of the semiconductor device formedas above, as shown in FIG. 5, concentration rises gradually from a drainend portion A of a channel side to the N+ type drain region 10. Asconcentration of the end portion A of the low concentration N type drainregion 5 becomes low (concentration of the N− type drain region 5Abecomes lower than concentration of the N− type drain region 5B),voltage between source and drain (BVDS) is maintained and operationsustaining voltage (VSUS) is improved.

[0059] Thus, by ion-implanting for forming low concentration drainregion before field oxidation, the low concentration N type drain region5 having concentration distribution at under part of the first gateinsulation film 4 and the active region is formed so that operationefficiency is good.

[0060] An another embodiment of the invention will be described.

[0061] First, the second embodiment is useful in case to raise moreoperation sustaining voltage (VSUS) in the semiconductor device of theabove-mentioned first embodiment. As shown in FIG. 6, by forming an Ntype layer 11 which is lower in concentration than the N+ type drainregion 10 and higher than said N− type drain region 5B (so called middleconcentration) so as to surround the N+ type drain region 10, operationsustaining voltage (VSUS) is further improved.

[0062] In the method of manufacturing the semiconductor device of theembodiment, by ion-implanting phosphorus ion (³¹P⁺) into a formingregion of said drain region 5 with about 160 KeV in acceleration voltageand about 2×10¹²/cm² in implantation volume as shown in FIG. 6 after themethod of manufacturing the semiconductor device of the above-mentionedfirst embodiment (processes of FIG. 1 to FIG. 4), the N type layer 11 isformed.

[0063] By the process, the N+ type drain region 10 is surrounded by theabove-mentioned N type layer 11 maintaining concentration of channelside drain region end portion low concentration by the N-type drainregion 5A. AS described above, by surrounding said high concentration N+drain region 10 with the middle concentration N type layer 11 and byletting depletion layer not extend to the N+ type drain region, thesemiconductor device of the invention removes double humpscharacteristic and can decrease substrate current (ISub) at high gatevoltage (VG) region as shown with a solid line in FIG. 7. Thus,operation sustaining voltage (VSUS) improves as shown in FIG. 8 and FIG.9. Especially, sustaining voltage improves extremely at high gatevoltage (VG) and high drain current (ID).

[0064] Next, a third embodiment of the invention will be described.

[0065] The characteristic of the semiconductor device of the thirdembodiment is that a middle concentration N type layer 11A is formedhaving the predetermined space (L) from one end portion (drain side) ofthe gate electrode 7 through said first gate insulation film 4 as shownin FIG. 10. Since electric field concentration at the end portion of thegate electrode 7 by forming the N type layer 11A having thepredetermined space (L) from one end portion the gate electrode 7,higher sustaining voltage is designed.

[0066] In the above-mentioned method of manufacturing the semiconductordevice, in the process of FIG. 6 described at the above-mentioned secondembodiment, a middle concentration N type layer 11A is formed near theN+ type drain region 10 included in said N− type drain region having thepredetermined space (L) from one end portion of said gate electrode 7 asshown in FIG. 10 by ion-implanting phosphorus ion (³¹P⁺), for example,with about 160 KeV in acceleration voltage and about 2×10¹²/cm² inimplantation volume forming a photo-resist 12 so as to overlap with thepredetermined space from the one end portion (drain side) of the gateelectrode. Therefore, a space from the gate electrode 7 (L) can be setfreely by adjusting overlap quantity to the gate electrode 7 through thefirst gate insulation film 4 at forming the photo-resist 12.

[0067] An another embodiment forming the above-mentioned middleconcentration N type layer having the predetermined space from one end(drain side) of the gate electrode 7 through the above-mentioned firstgate insulation film 4 will be described.

[0068] First, in a fourth embodiment, the above-mentioned constructionis realized by forming a side wall insulation film 13 so as to cover aside wall portion of the first gate insulation film 4 ion-implanting forforming N type layer by using a side wall insulation film 13 as a maskas shown in FIG. 11.

[0069] That is, after process of FIG. 4 described in the firstembodiment, an insulation film is formed by CVD method. After that, theside wall insulation film 13 is formed at a gate electrode 7 and a sidewall portion of the first gate insulation film 4 by isotropic etchingthe insulation film.

[0070] Then, a middle concentration N type layer 11B is formed near theN+ type drain region 10 included in said N− type drain region 5B havingthe predetermined space (L) from the other end portion of said gateelectrode 7 by ion-implanting phosphorus ion (³¹P⁺), for example, withabout 160 KeV in acceleration voltage and about 2×10¹²/cm² inimplantation volume by using said first gate insulation film 4 and theside wall insulation film 13 as a mask.

[0071] Thus, in the fourth embodiment, since the side wall insulationfilm 13 formed at the side wall portion of the first gate insulationfilm 4 instead of the photo-resist 12 such as the second embodiment isused for a part of a mask, positioning margin of forming the N typelayer to the gap of mask matching worried at using the photo-resist 12can be ensured. That is, in the embodiment, a space (L) from the endportion of the gate electrode 7 to the position forming the N type layer11B can be adjusted freely by thickness of the insulation film forforming the side wall insulation film.

[0072] Further, a fifth embodiment will be described.

[0073] Here, a characteristic of the fifth embodiment is that theabove-mentioned construction is realized by ion implantation for formingthe N type layer from oblique upper side of the first gate insulationfilm 4 by using the first gate insulation film 4 as a mask after formingthe gate electrode 4 as shown in FIG. 12.

[0074] That is, a middle concentration N type layer 11C is formed nearthe N+ type drain region 10 included in said N− type drain region 5Bhaving the predetermined space (L) from the other end portion of saidgate electrode 7 by ion-implanting phosphorus ion (³¹P⁺), for example,with about 160 KeV in acceleration voltage and about 2×10¹²/cm² inimplantation volume from oblique upper side of the first gate insulationfilm 4 by using the first gate insulation film 4 on the gate insulationfilm 3 as a mask after the process of FIG. 4 described in the firstembodiment. At this time, depending on thickness of the first gateinsulation film 4, a space (L) from the end portion of the gateelectrode 7 to the position where the N type layer 11C is formed isadjusted freely by adjusting ion adjusting angle from oblique upper sideof the first gate insulation film 4 (ion implantation of 30 degrees ofoblique angle from vertical direction in the embodiment) freely.

[0075] Thus, in the fifth embodiment, the N type layer 7D having thepredetermined space (L) from the gate electrode 7 can be formed by ionimplantation from oblique upper side of the first gate insulation film4, and number of manufacturing processes can be decreased comparing withmanufacturing method using the photo-resists PR2 and the side wallinsulation film 13. Moreover,a space (L) from the end portion of thegate electrode 7 to the position where the N type layer 11C is formedcan be adjusted only by adjusting freely ion implantation angle at ionimplantation, so that operation efficiency is good.

[0076] In the process using such the oblique ion implantation method,ion implantation may be carried out from oblique direction using aphoto-resist 12 as the above-mentioned second embodiment though thedescription shown in a figure is omitted. Further, ion implantation maybe carried out from oblique direction using said side wall insulationfilm 13 as the third embodiment instead of the photo-resist 12.

[0077] According to the invention, since the lower concentration reverseconductive type drain region differ in high impurity concentrationbetween the under part of the gate electrode through the first gateinsulation film and the active region is formed, electric fieldconcentration to the end portion of the gate electrode through the firstgate insulation film is controlled so as to improve operation sustainingvoltage.

[0078] The semiconductor device has high impurity concentration peak atthe position of the predetermined depth in the substrate at region whereis separated from the other end of the gate electrode and spans to ahigh concentration reverse conductive type drain region included in alow concentration reverse conductive type drain region, and forms amiddle concentration reverse conductive type layer becoming low in highimpurity concentration at region near surface of the substrate.Therefore, operation sustaining voltage further improves.

[0079] Especially, by forming said middle concentration reverseconductive type layer at the position separated the predetermined spacefrom the end portion of the gate electrode through said first gateinsulation film, higher sustaining voltage becomes possible.

What is claimed is:
 1. A semiconductor device comprising: a gateelectrode formed extending on a first and second gate insulation filmsformed on one conductive type semiconductor substrate; a reverseconductive type source region adjacent to one end of said gateelectrode; a first low concentration reverse conductive type drainregion formed facing said source region through a channel region, havinghigh impurity concentration peak at a position of the predetermineddepth at least in said substrate under said first gate insulation film,and formed so that high impurity concentration becomes low at a regionnear surface of the substrate; a second concentration reverse conductivetype drain region formed so as to range to the first low concentrationreverse conductive type drain region; and a third concentration reverseconductive type drain region separated from the other end of said gateelectrode and included in said second concentration reverse conductivetype drain region.
 2. A semiconductor device comprising: a gateelectrode formed extending on a first and second gate insulation filmsformed on one conductive type semiconductor substrate; a reverseconductive type source region adjacent to one end of said gateelectrode; a first low concentration reverse conductive type drainregion formed facing said source region through a channel region, havinghigh impurity concentration peak at a position of the predetermineddepth at least in said substrate under said first gate insulation film,and formed so that high impurity concentration becomes low at a regionnear surface of the substrate; a second concentration reverse conductivetype drain region formed so as to range to the first low concentrationreverse conductive type drain region; a third concentration reverseconductive type drain region separated from the other end of said gateelectrode and included in said second concentration reverse conductivetype drain region; and a fourth concentration reverse conductive typelayer formed so as to span from one end portion of said first gateinsulation film to said third concentration reverse conductive typedrain region.
 3. A semiconductor device according to claim 1, whereinsaid first insulation film is a field oxidation film field-oxidized. 4.A semiconductor device according to claim 1, wherein said fourthconcentration reverse conductive type layer has high impurityconcentration peak at a position of the predetermined depth in saidsubstrate at a region spanning from a position having the predeterminedspace from one end portion of said first gate insulation film to saidthird concentration reverse conductive type drain region, and is formedso that high impurity concentration becomes low at a region near surfaceof the substrate.
 5. A method of manufacturing a semiconductor devicecomprising the steps of: ion-implanting a reverse conductive typeimpurity in the predetermined region of one conductive typesemiconductor substrate; forming a first gate insulation film, a firstconcentration reverse conductive type drain region under the first gateinsulation film, and a second concentration reverse conductive typedrain region so as to range to the first concentration reverseconductive type drain region by diffusing said impurity ion-implanted ina heat treatment for field-oxidizing the predetermined region of saidsubstrate; forming a gate electrode so as to span from the first gateinsulation film to the second gate insulation film after forming thesecond gate insulation film on said substrate except said first gateinsulation film; and forming a reverse conductive type source region soas to be adjacent to one end of said gate electrode, and forming a thirdconcentration reverse conductive type drain region facing said sourceregion through a channel region, separated from the other end of saidgate electrode, and included in said second concentration reverseconductive type drain region.
 6. A method of manufacturing asemiconductor device according to claim 5, wherein said step of forminga first concentration reverse conductive type drain region and secondconcentration reverse conductive type drain region comprises a step ofdiffusing said impurity ion so that the impurity ion-implanted is takenin the first gate insulation film at field oxidation.
 7. A method ofmanufacturing a semiconductor device according to claim 5, furthercomprising: forming a fourth concentration reverse conductive type layerso as to span from one end portion of said first gate insulation film tosaid third concentration reverse conductive type drain region.
 8. Amethod of manufacturing a semiconductor device according to claim 5,further comprising: forming a fourth concentration reverse conductivetype layer having high impurity concentration peak at a position of thepredetermined depth in said substrate at a region spanning from aposition having the predetermined space from one end portion of saidfirst gate insulation film to said third concentration reverseconductive type drain region, and is formed so that high impurityconcentration becomes low at a region near surface of the substrate. 9.A method of manufacturing a semiconductor device according to claim 7,wherein phosphorus ion is ion-implanted with high acceleration energy ofabout 100 KeV to 200 KeV at said forming process of the fourthconcentration reverse conductive type layer.
 10. A method ofmanufacturing a semiconductor device according to claim 8, whereinphosphorus ion is ion-implanted with high acceleration energy of about100 KeV to 200 KeV at said forming process of the fourth concentrationreverse conductive type layer.
 11. A method of manufacturing asemiconductor device according to claim 7, wherein ion implantation iscarried out at a region spanning from a position separated thepredetermined space from said first gate insulation film to said thirdconcentration reverse conductive type drain region by using aphoto-resist as a mask at said forming process of the fourthconcentration reverse conductive type layer.
 12. A method ofmanufacturing a semiconductor device according to claim 8, wherein ionimplantation is carried out at a region spanning from a positionseparated the predetermined space from said first gate insulation filmto said third concentration reverse conductive type drain region byusing a photo-resist as a mask at said forming process of the fourthconcentration reverse conductive type layer.
 13. A method ofmanufacturing a semiconductor device according to claim 7, wherein ionimplantation is carried out at a region spanning from a positionseparated the predetermined space from the first gate insulation film tosaid third concentration reverse conductive type drain region by using aside wall insulation film formed at a side wall portion of said firstgate insulating film as a mask at said forming process of the fourthconcentration reverse conductive type layer.
 14. A method ofmanufacturing a semiconductor device according to claim 8, wherein ionimplantation is carried out at a region spanning from a positionseparated the predetermined space from the first gate insulation film tosaid third concentration reverse conductive type drain region by using aside wall insulation film formed at a side wall portion of said firstgate insulating film as a mask at said forming process of the fourthconcentration reverse conductive type layer.
 15. A method ofmanufacturing a semiconductor device according to claim 7, wherein saidfourth concentration reverse conductive type layer is formed at a regionspanning from a position separated the predetermined space from thefirst gate insulation film to said third concentration reverseconductive type drain region by ion-implanting from oblique upper sideof the first gate insulation film by using said first gate insulationfilm as a mask at said forming process of the fourth concentrationreverse conductive type layer.
 16. A method of manufacturing asemiconductor device according to claim 8, wherein said fourthconcentration reverse conductive type layer is formed at a regionspanning from a position separated the predetermined space from thefirst gate insulation film to said third concentration reverseconductive type drain region by ion-implanting from oblique upper sideof the first gate insulation film by using said first gate insulationfilm as a mask at said forming process of the fourth concentrationreverse conductive type layer.
 17. A method of manufacturing asemiconductor device according to claim 7, wherein said fourthconcentration reverse conductive type layer is formed at a regionspanning from a position separated the predetermined space from thefirst gate insulation film to said third concentration reverseconductive type drain region by ion implantation from oblique upper sideby using a photo-resist formed so as to cover said first gate insulationfilm as a mask at said forming process of the fourth concentrationreverse conductive type layer.
 18. A method of manufacturing asemiconductor device according to claim 8, wherein said fourthconcentration reverse conductive type layer is formed at a regionspanning from a position separated the predetermined space from thefirst gate insulation film to said third concentration reverseconductive type drain region by ion implantation from oblique upper sideby forming a photo-resist formed so as to cover said first gateinsulation film as a mask at said forming process of the fourthconcentration reverse conductive type layer.
 19. A method ofmanufacturing a semiconductor device according to claim 7, wherein highimpurity concentration of said first concentration reverse conductivetype drain region is formed so as to become lower than said secondconcentration reverse conductive type drain region by that said impurityion-implanted is taken in the first gate insulation film at fieldoxidation.
 20. A method of manufacturing a semiconductor deviceaccording to claim 8, wherein high impurity concentration of said firstconcentration reverse conductive type drain region is formed so as tobecome lower than said second concentration reverse conductive typedrain region by that said impurity ion-implanted is taken in the firstgate insulation film at field oxidation.